Active current mode sampling circuit

ABSTRACT

The invention relates to an active current mode sampling circuit comprising an operational amplifier ( 103 ) and at least one switched capacitor (C 2   , C   2   a, C   2   b ). In order to reduce the power consumption of such a circuit, first switching elements (S 101   a, S   101   b, S   102   a, S   102   b ) switch the switched capacitor (C 2   , C   2   a, C   2   b ) between an input and an output of the operational amplifier ( 103 ) during charging phases φ 1 . Further, second switching elements (S 103   a, S   103   b, S   104   a, S   104   b ) connect the switched capacitor (C 2   , C   2   a, C   2   b ) during discharging phases φ 2  to a subsequent stage ( 104 ), in order to provide a charge of the switched capacitor (C 2   , C   2   a, C   2   b ) to the subsequent stage ( 104 ). The invention relates equally to a device ( 107 ) comprising such a sampling circuit and to a method of operating such a sampling circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This is the U.S. National Stage of International Application No.PCT/IB2003/004246 filed Sep. 29, 2003 and published in English on Apr.7, 2005 under International Publication No. WO 2005/031755 A1.

FIELD OF THE INVENTION

The invention relates to an active current mode sampling circuitcomprising an operational amplifier and at least one switched capacitor.The invention relates equally to a device comprising such a samplingcircuit and to a method of operating such a sampling circuit.

BACKGROUND OF THE INVENTION

Sampling circuits are known from the state of the art. A samplingcircuit can be employed for example in a receiver for sampling receivedsignals.

A conventional receiver is usually implemented with complicated analogtechniques and using BiCMOS (bipolar complementary metal-oxidesemiconductor) or other analog-oriented semiconductor.

For illustration, a block diagram of an exemplary analog directconversion receiver is presented as FIG. 1.

The depicted receiver comprises a low noise amplifier (LNA) 10 foramplifying received radio frequency (RF) signals, mixers 11 fordownconverting the amplified RF signals, an analog signal processingcomponent 12 for processing the downconverted signals, analog-to-digitalconverters (ADC) 13 for converting the processed analog signals intodigital signals, and a digital signal processing component (DSP) 14 forfurther processing of the digital signals. For processing the analogdownconverted signal, the analog signal processing component 12comprises an Nth-order low-pass filter (LPF), an analog gain control(AGC), a direct-current (DC) offset cancellation, etc. For processingthe digital signal, the DSP 14 comprises a decimation stage, an LPF,etc. The output of the DSP 22 constitutes the digital baseband (BB)output.

This kind of receiver requires high-order analog base band filters toattenuate undesired signals, and at the same time, it has a high in-bandamplification. Depending on the involved system, e.g., GSM (globalsystem for mobile communications), CDMA (code division multiple access),WCDMA (wideband CDMA), etc., up to seventh-order analog filters may berequired. In addition to the complicated filter, also an accurate AGC isneeded in order to relax ADC requirements in terms of samplingfrequency, dynamic range and related silicon costs. To this end, a largenumber of high quality resistors and capacitors is needed in theimplementation. Due to large temperature dependency and processvariations of the resistor-capacitor (RC) time constants, often somekind of calibration or tuning is required in addition. Moreover, highquality resistors require additional mask layers, which also increasethe costs of the production process.

Due to cost reasons, it is therefore often desirable to increase theintegration level by digitalization, that is, to implement RF receiversand analog input interface circuits in a pure digital semiconductorprocess, for example in a deep sub-micron CMOS, together with thedigital signal processing blocks. Also to support this trend, circuittechniques are being developed that enable signal processing functions,which are conventionally implemented in the analog domain, likefiltering, to be implemented with digital techniques.

A block diagram of a more digital implementation of a direct conversionreceiver is presented as FIG. 2.

The receiver of FIG. 2 comprises again an LNA 20 for amplifying receivedRF signals. Further, it comprises a first integrated processingcomponent 21 for processing the received analog signals. This processingincludes a frequency down conversion, an analog pre-filtering and ananalog-to-digital conversion by ADCs. The receiver comprises in additiona DSP 22 for processing the resulting digital signals. The DSP 22realizes more specifically a decimation, a low-pass filtering, anautomatic gain control, a direct-current (DC) offset cancellation, etc.The output of the DSP 22 constitutes the digital baseband (BB) output.

The benefits of the digitalization of the RF and analog interfacecircuits include an increased integration level, a size reduction withtime through process technology shrinkage, an increased flexibility andadaptability of the circuits, shorter design cycles which are madepossible through design synthesis, portability and reuse of thecircuits, an ease of the implementation of the complex signal processingin the digital domain, less calibration in the production, and a bettercontrol of performance.

One approach for realizing a digitalization of an RF receiver isutilizing a subsampling technique, where the frequency downconversionand the sampling are combined and performed by a voltage mode samplingoperation. This solution, however, has the drawback that it still needsa continuous time antialias filter. Actually, a voltage mode samplingoperation makes the antialias filter implementation even morecomplicated compared to the conventional direct conversion RF receiver,because it requires a very selective bandpass filter at the RFfrequencies.

A more promising approach for realizing a digitalization of an RFreceiver by a system-on-chip (SoC) solution is utilizing a current modesampling operation, which is also called charge sampling. The currentmode sampling has several advantages over the voltage mode sampling. Acurrent mode sampling operation contains an inherent antialiasfiltering. Therefore the additional antialias filter needed inconventional voltage mode sampling can be avoided. The antialias filterfrequency response does not have to be calibrated, because it isproportional to the capacitor ratio and the clock frequency, which areamong the best-controlled parameters in the analog semiconductorintegration. A current mode sampling operation is moreover suitable foran implementation with a pure digital deep-submicron CMOS process,because additional mask layers needed for high quality resistors can beavoided. Further, the frequency down-conversion can be combined easilywith the current mode sampling circuit.

The operational principle of a current mode sampling without frequencydown-conversion is illustrated by the schematic circuit of FIG. 3. Thecircuit comprises a transconductance element (GM) 30, which is connectedvia a first switching element S31 and a second switching element S32 toan output. Between the first switching element S31 and the secondswitching element S32, a sampling capacitor C30 and a third switchingelement 33 are connected in parallel to each other to ground.

The transconductance element 30 converts an input voltage mode signalVIN into a current mode signal. The first switching element S31 isclosed during an integration period φ1, and the current mode signal isintegrated by the sampling capacitor C30 during this integration periodφ1. After the integration period φ1, the resulting voltage acrosscapacitor C30 is then sampled by the subsequent stages for furtherprocessing. The resulting voltage VOUT is provided to subsequent stagesmore specifically by closing the second switching element S32 during adischarging period φ2. Before the next integration period φ1 is enteredfor a new sample, the sampling capacitor C30 is reset by closing thethird switching element S33.

FIG. 4 presents a current mode sampling circuit with frequencydown-conversion, in which a transconductance element 40, switchingelements S41, S42 and S43 and a sampling capacitance C40 are arranged inthe same manner as in FIG. 3. In the circuit of FIG. 4, however, aswitching element S44, which performs the frequency down-conversion, isinserted between the transconductance element 40 and the actual samplingcircuit with elements C40, S41, S42 and S43. The switching element S44is controlled by a local oscillator signal LO.

The transconductance element 40 converts an input RF voltage mode signalVRF into a current mode signal. The resulting current mode signal isthen frequency down-converted by the switching element S44. The purposeof the down-conversion is to bring the current signal provided by thetransconductance element 40 from the radio frequency down to a frequencyrange in which it can be sampled with sufficient performance, e.g. to anintermediate frequency (IF) or to the base band (BB), as indicated inthe diagram of FIG. 5. The subsequent sampling is the same as in thecircuit of FIG. 3. That is, switching element S41 is closed duringintegration periods φ1 such that the current mode signal is integratedby the sampling capacitor C40. The resulting BB or IF voltage VBB/VIFacross capacitor C40 is provided to subsequent stages by closing thesecond switching element S42 during discharging periods φ2. Before thenext integration period φ1, the sampling capacitor C40 is reset byclosing the third switching element S43.

Such a current mode sampling has been presented for example by JirenYuan in: “A Charge Sampling Mixer With Embedded Filter Function forWireless Applications”, 2nd International Conference on Microwave andMillimeter Wave Technology Proceedings, 2000, by Karvonen S. in:“Analysis and Realization of a Downconverting Quadrature Sampler”,Diploma Thesis, University of Oulu, 2001, by Karvonen S., Riley T. andKostamovaara J. in: “A Low Noise Quadrature Subsampling Mixer”, IEEEInternational Symposium on Circuits and Systems 2001, Volume 4, and byKarvonen S., Riley T. and Kostamovaara J. in: “Charge Sampling MixerWith DS Quantized Impulse Response”, IEEE International Symposium onCircuits and Systems 2002, volume 1.

The integration of a current mode signal over a given period of timeproduces a SINC=sin(x)/x type of frequency domain transfer function,which has transmission zeros at the sampling frequency Fs and itsmultiples 2Fs, 3Fs, etc. Thus, the transfer function zeros create aninherent anti-alias filter for the sampling operation. That is, foldinginterferences and noise are filtered due to the inherent antialiasfiltering. The transfer function and the aliasing of the current modesampling are sketched in FIG. 6. As can be seen, the transfer functionhas a significant attenuation of the aliasing frequency bands, i.e.around the zeros at Fs, 2Fs, 3Fs, etc., especially near the samplingfrequency Fs. Therefore, a current mode sampling is well suited for usewith over-sampling ADCs, in which the signal band is narrow compared tothe sampling frequency.

On the whole, it is to be understood that the current mode sampling doesnot constitute a kind of sub-sampling, and thus, it does not have theproblems associated with, for example, voltage mode RF sub-sampling.

FIG. 7 presents a straightforward implementation of the passive currentmode sampling with frequency down conversion as shown in FIG. 4. In FIG.7, the passive current mode sampling and the frequency down conversionare further combined with a switched-capacitor integrator for low-passfiltering.

The circuit of FIG. 7 thus comprises a transconductance element 70, afrequency down-conversion portion 71, a sampling portion 72 and an LPFportion 75.

The transconductance element 70 has two inputs and two outputs, thelatter being connected to the frequency down-conversion portion 71. Thefrequency down-conversion portion 71 comprises four switches which arecontrolled by a local oscillator.

In the sampling portion 72, a first path is realized, which connects afirst output of the frequency down-conversion portion 71 via a switchS71 a, a sampling capacitor Csa and a switch S72 a to a first output ofthe sampling portion 72. In this first path, the first output of thefrequency down-conversion portion 71 is further connected via acapacitor Cia to ground Vcm. In addition, the connection between switchS71 a and capacitor Csa is connected via a switch S73 a to ground Vcm,while the connection between capacitor Csa and switch S72 a is connectedvia a switch S74 a to ground Vcm. The second output of the frequencydown-conversion portion 71 is connected in exactly the same manner via asecond path realized in the sampling portion 72 to a second output ofthe sampling portion 72. In the second path, corresponding capacitorsare named Csb and Cib instead of Csa and Cia, respectively, andcorresponding switches are named S71 b to S74 b instead of S71 a to S74a, respectively.

The capacitors Csa and Csb and the switches S71 a to S74 a and S71 b toS74 b of the first and the second path form a first sampler 73.Additionally, identical samplers 74 etc. may be connected in parallel tothe first sampler 73.

The LPF portion 75 comprises an operational amplifier 76.

The first output of the sampling portion 72 is connected via a firstinput of the LPF portion 75 to a first input of operational amplifier76, and a first output of operational amplifier 76 is connected to afirst output of the LPF portion 75. A capacitor C1 a on the one hand anda series connection of a switch S75 a, a capacitor C2 a and a switch S76a on the other hand are arranged in parallel to each other between thefirst input and the first output of operational amplifier 76. Theconnection between switch S75 a and capacitor C2 a is connected via aswitch S77 a to ground Vcm, while the connection between capacitor C2 aand switch S76 a is connected via a switch S78 a to ground Vcm.

The second output of the sampling portion 72 is connected to a secondinput of the LPF portion 75. The second input and output of operationalamplifier 76 are connected to the second input of the LPF portion 75 anda second output of the LPF portion 75, respectively, and correspondingcomponents are connected directly and indirectly to the second input andoutput of operational amplifier 76 as to the first input and output ofoperational amplifier 76. Corresponding capacitors are named C1 b and C2b instead of C1 a and C2 a, respectively, and corresponding switches arenamed S75 b to S78 b instead of S75 a to S78 a, respectively.

Transconductance element 70 converts two input RF voltage mode signalsinto RF current mode signals and provides them to the frequency downconversion portion 71. A separate LNA (not shown) can be used in frontof transconductance element 70. Alternatively, the transconductanceelement 70 could be either an integral part of an LNA or of thefrequency down-conversion portion 71. However, in any implementation oneor more semiconductor devices can be recognized that provide thefunction of a transconductor.

The local oscillator provides alternating signals LO+ and LO− to theswitches of the frequency down conversion portion 71. When the LO+signal is active, the outputs of the transconductance element 70 areconnected to the sampling portion 72 in a direct way, i.e. the firstoutput of the transconductance element 70 is connected to the first pathof the sampling portion 72, while the second output of thetransconductance element 70 is connected to the second path of thesampling portion 72. When the LO− signal is active, the outputs of thetransconductance element 70 are connected to the sampling portion 72 ina cross-coupled way, i.e. the first output of the transconductanceelement 70 is connected to the second path of the sampling portion 72,while the second output of the transconductance element 70 is connectedto the first path of the sampling portion 72. With this operation, theRF current signals output by the transconductance element 70 arefrequency down-converted into IF current signals.

In the sampling portion 72, switches S71 a, S74 a, S71 b and S74 b areclosed during a clock phase φ1, while switches S72 a, S73 a, S72 b andS73 b are closed during a clock phase φ2. Clock phases φ1 and φ2 arealternating with each other.

The signal current is thus integrated by the sampling capacitors Csa andCsb during a respective clock phase φ1. The sampling is said to bepassive, as no operational amplifier participates in the integration.The sampling capacitors Csa and Csb are then discharged to zero during acharge transfer from the capacitors Csa and Csb to the LPF portion 76during a respective clock phase φ2. Therefore, an additional reset phaseis not needed for discharging the switched capacitors Csa and Csb beforethe respective next sampling phase. The capacitors Cia and Cib areneeded to avoid a shifting of the transfer function zeros due to thenon-overlap time of the sampling. In addition, the capacitors Cia andCib are also used to attenuate RF blockers and interferences.

Alternatively, switches S71 a, S72 a, S71 b and S72 b could be closedduring a clock phase φ1, while switches S73 a, S74 a, S73 b and S74 bare closed during a clock phase φ2. In this case, the charge transfer tothe LPF portion 76 takes place during the charging of the capacitors Csaand Csb in a respective clock phase φ1, while clock phase φ2 is a puredischarging phase.

Parallel samplers 74 can be used in order to reduce the sampling clockfrequency or to build an analog FIR (finite impulse response) filtersampling stage.

The LPF portion 75 then performs a low-pass filtering on the receivedcurrent samples. To this end, switches S75 a, S76 a, S75 b and S76 b areclosed in the respective clock phase φ1, while switches S77 a, S78 a,S77 b and S78 b are closed in the respective clock phase φ2.

The power consumption of operational amplifier 76 of the LPF portion 75can be reduced by a modification as presented in FIG. 8.

The circuit of FIG. 8 comprises exactly the same components as thecircuit of FIG. 7, except that the capacitors C2 a and C2 b and theswitches S75 a to S78 a and S75 b to S78 b are removed. Moreover, switchS73 a in the first depicted path of the sampling portion 72 is no longerconnected to ground Vcm, but instead to the first output of operationalamplifier 76. The connection between switch S73 a and the capacitor Csais connected within the sampling portion 72 via a switch S81 a to theconnection between switch S74 a and the capacitor Csa. A correspondingarrangement is introduced between the second output of operationalamplifier 76 and the second depicted path in the sampling portion 72,including switch S81 b. The outputs of the operational amplifier 76 aremoreover connected in the same manner in parallel to the first and thesecond paths in any possible further sampler 74.

The sampling operation is similar to the sampling operation in thecircuit of FIG. 7. In this case, however, capacitors Csa and Csb arecharged during a respective clock phase φ1, connected to operationalamplifier 76 during a respective clock phase φ2, and discharged during arespective additional reset clock phase φr by closing switches S81 a andS81 b.

Compared to the circuit of FIG. 7, a lower power consumption isachieved, since the workload of operational amplifier 76 is relaxed inthe charge transfer clock phase φ2 due to the modified switchingtopology. The main drawback of this circuit is, however, that theadditional reset clock phase φr is needed for discharging the switchedcapacitors Csa and Csb before the respective next sampling. Due to theadditional reset clock phase φr, parallel samplers 74 are required inaddition to sampler 73.

In a passive current mode sampling, the current consumption of theoperational amplifier of an LPF portion could also be reduced by meansof a decimation circuit as presented by S. Lindfors in: “CMOS BasebandIntegrated Circuit Techniques for Radio Receivers”, doctoral thesis,Helsinki University of Technology, July 2000. In that topology, thesampling frequency of a switched capacitor connected to the operationalamplifier can be smaller than the input sampling frequency of thecurrent mode sampling, resulting in lower bandwidth requirements for theoperational amplifier.

A serious drawback of a passive current mode sampling in general,however, results from the common use of transistors as switches.

Transistors in modern semiconductor processes have a low outputimpedance, such that also the employed transconductance elements in thepresented circuits have a low output impedance. This low outputimpedance causes a leakage of the transfer function zeros and thusdegrades the advantageous anti-alias filter properties of the currentmode sampling. The problem becomes severe, when the passive current modesampling is implemented using components available in digital deep-submicron CMOS processes, where the output impedance of the realizedcomponents is inherently low.

Another serious drawback resulting from the low output impedance is poorlinearity for the third order intercept point, IIP3. As the integratedvoltage in the sampling capacitors, and thus the voltage at the outputof the mixer and in some cases also of the transconductance element, isa function of the input signal, a signal dependent distortion isintroduced due to channel modulation effects in the mixing transistorsof the frequency down-conversion portion.

A known circuit topology that circumvents the problem resulting from thelow output impedance of the transconductance element and from thenon-linearity of the transistors mixing the RF signal is shown in FIG.9, which enables an active current mode sampling instead of a passivecurrent mode sampling.

The circuit of FIG. 9 comprises as well a transconductance element 90for converting RF voltage mode signals into RF current mode signals anda frequency down-conversion portion 91 for frequency down-converting theRF current signals into IF current signals, as described above withreference to FIG. 7. In addition, the circuit of FIG. 9 comprises asampling and LPF portion 92 and a following switched-capacitor (SC)block 94 realizing a part of an ADC or an SC-filter.

The sampling and LPF portion 92 comprises an operational amplifier 93.The first output of the frequency down-conversion portion 91 isconnected via a first input of the sampling and LPF portion 92 to afirst input of operational amplifier 93, and a first output ofoperational amplifier 93 is connected to a first output of the samplingand LPF portion 92. A capacitor C1 a on the one hand and a seriesconnection of a switch S91 a, a capacitor C2 a and a switch S92 a on theother hand are arranged in parallel to each other between the firstinput and the first output of operational amplifier 93. The connectionbetween switch S91 a and capacitor C2 a is connected via a switch S93 ato ground Vcm, while the connection between capacitor C2 a and switchS92 a is connected via a switch S94 a to ground Vcm.

The second output of the frequency down-conversion portion 91 isconnected to a second input of the sampling and LPF portion 92. A secondinput and output of operational amplifier 93 are connected to the secondinput of the sampling and LPF portion 92 and a second output of thesampling and LPF portion 92, respectively, and corresponding componentsare connected directly and indirectly to the second input and output ofoperational amplifier 93 as to the first input and output of operationalamplifier 93. Corresponding capacitors are named C1 b and C2 b insteadof C1 a and C2 a, respectively, and corresponding switches are named S91b to S94 b instead of S91 a to S94 a, respectively.

The components of the sampling and LPF portion 92 form an activeswitched-capacitor integrator.

The first output of the sampling and LPF portion 92 is connected withinthe SC block 94 via a switch S95 a, a sampling capacitor C4 a and aswitch S96 a to a first input of an operational amplifier 95. Inaddition, the connection between switch S95 a and capacitor C4 a isconnected via a switch S97 a to ground Vcm, while the connection betweencapacitor C4 a and switch S96 a is connected via a switch S98 a toground Vcm. The second output of the of the sampling and LPF portion 92is connected within the SC block 94 in exactly the same manner to asecond input of operational amplifier 95. A corresponding capacitor isnamed C4 b instead of C4 a, and corresponding switches are named S95 bto S98 b instead of S95 a to S98 a, respectively.

A respective capacitor C3 a, C3 b is arranged between the first inputand a first output of the operational amplifier 95 and between thesecond input and a second output of the operational amplifier 95.Further elements may be connected in parallel to the respectivecapacitor C3 a, C3 b for realizing the desired functions.

In the sampling and LPF portion 92, switches S91 a, S92 a, S91 b and S92b are closed during a clock phase φ1, while switches S93 a, S94 a, S93 band S94 b are closed during a clock phase φ2. Capacitors C2 a and C2 bare therefore charged during a respective clock phase φ1 and dischargedto zero during a respective clock phase φ2, the latter constituting adedicated reset clock phase. Clock phases φ1 and φ2 are alternating witheach other.

The current mode signals provided by the frequency down-conversionportion 92 are thus integrated by the active switched-capacitorintegrator of the sampling and LPF portion 92, which provides a virtualshort circuit at the sampler input. The switched-capacitor integratordoes not allow the output voltage of the frequency down conversionportion 91 and, in some cases, of the transconductance element 90 tovary, as the signals are in a current mode. Therefore, a leakage of thetransfer function zeros due to the small output impedance is eliminatedand better quality anti-alias filtering properties are obtained. Inaddition, as the voltage swing is practically negligible, a betterlinearity (IIP3) is obtained. With the shown switched-capacitorintegrator, or alternatively with another higher order filter, also theRF blockers are attenuated.

In the SC block 94, switches S95 a, S96 a, S95 b and S96 b are closedduring a clock phase φ1, while switches S97 a, S98 a, S97 b and S98 bare closed during a clock phase φ2. Sampling capacitors C4 a and C4 bare therefore charged during the respective clock phase φ1 anddischarged to zero during the respective clock phase φ2. The sampledsignal is then further processed as desired by the operational amplifier95.

It is a disadvantage of the circuit of FIG. 9 that it involves a highpower consumption as, for example, power is wasted during the resetclock phase φ2. The power consumption is heavily dependent on theswitching frequency and on the capacitance values of capacitors C2 a andC2 b on the one hand and C4 a and C4 b on the other hand. The problem isthat while it is desirable to have a low switching frequency forachieving a low power consumption, it is desirable to have a highswitching frequency for a wide bandwidth of the transfer function zerosrelative to the signal bandwidth.

Due to the high power consumption, an active current mode sampling iscurrently only used for sampling an IF input signal, as described in theabove mentioned document “A Charge Sampling Mixer With Embedded FilterFunction for Wireless Applications”.

SUMMARY OF THE INVENTION

It is an object of the invention to enable an improved active currentmode sampling. It is in particular an object of the invention to reducethe power consumption of active current mode sampling circuits. It isfurther an object of the invention to reduce the noise in an activecurrent mode sampling.

An active current mode sampling circuit is proposed which comprises anoperational amplifier, at least one switched capacitor and firstswitching elements for switching the at least one switched capacitorbetween an input and an output of the operational amplifier duringcharging phases and for disconnecting the at least one switchedcapacitor from the input and the output of the operational amplifier inbetween the charging phases. The proposed active current mode samplingcircuit further comprises second switching elements for connecting theat least one switched capacitor during discharging phases in between thecharging phases to a subsequent stage, in order to provide a charge ofthe at least one switched capacitor to the subsequent stage, and fordisconnecting the at least one switched capacitor from the subsequentstage in between the discharging phases.

Moreover, a device is proposed, which comprises the proposed activecurrent mode sampling circuit. The device can be for example a receiverof a radio system or a terminal comprising such a receiver.

Moreover, a method of operating an active current mode sampling circuitis proposed, which active current mode sampling circuit includes anoperational amplifier and at least one switched capacitor. The proposedmethod comprises switching the at least one switched capacitor betweenan input and an output of the operational amplifier during chargingphases. The proposed method further comprises disconnecting the at leastone switched capacitor from the input and the output of the operationalamplifier in between these charging phases. The proposed method furthercomprises connecting the at least one switched capacitor duringdischarging phases in between the charging phases to a subsequent stage,in order to provide a charge of the at least one switched capacitor tothis subsequent stage. Finally, the proposed method comprisesdisconnecting the at least one switched capacitor from the subsequentstage in between the discharging phases.

The invention proceeds from the consideration that the signal voltage atthe output of an operational amplifier is also available across aswitched capacitor which is connected during charging phases between aninput and an output of the operational amplifier. Therefore, it isproposed to use such a capacitor to transfer a charge to a followingstage within the active current mode sampling circuit or outside of theactive current mode sampling circuit. The operational amplifier and theswitched capacitor in the feedback path of the operational amplifier canbe for example part of a switched capacitor integrator realizing alow-pass filtering, and in the proposed configuration, the switchedcapacitor is used at the same time as sampling capacitor.

It is an advantage of the invention that it makes the capacitive loadingof the operational amplifier smaller, which results in a lower powerconsumption for a given sampling frequency. Alternatively, the samplingfrequency could be increased without increasing the power consumption.Due to the increased power efficiency, the possible operational area ofan active current mode sampling circuit is increased. It becomespossible, for example, to use an active current mode sampling circuit aswell for direct conversion receivers and broadband applications.Further, the lower power consumption enables an implementation in deepsub-micron semiconductor processes with low supply voltage. It may evenallow to integrate an entire receiver on a single chip.

It is further an advantage of the invention that the number ofcomponents of the sampling circuit is reduced, as an additional samplingcapacitor connected to an output of the operational amplifier is notrequired any more. As a result, the thermal noise power is lowercompared to the known active current mode sampling.

The proposed arrangement of the sampling switched capacitor in thefeedback path of the operational amplifier further ensures that thetotal noise is reduced, as the DC offset and the low frequency noise,for instance the flicker noise of the operational amplifier, see arelatively lower gain compared to the signal gain than in known activecurrent mode sampling circuits.

Just like the known active current mode sampling circuits, also theproposed active current mode sampling circuit ensures that the value andthus the area of the capacitors realizing a low-pass filter, e.g. a BBlow-pass filter, can be smaller compared to passive current modesampling and conventional mixer/filter interfaces.

Preferred embodiments of the invention become apparent from the detaileddescription below.

The proposed active current mode sampling circuit may comprise inaddition a transconductance portion converting an available voltage modesignal into a current mode signal, and a frequency down-conversionportion applying a frequency down-conversion on this current mode signalbefore providing it to the operational amplifier. Like the known activecurrent mode sampling circuit, the proposed configuration ensures a lowvoltage swing at the output of the transconductance portion and of thefrequency down-conversion portion, and a good linearity (IIP3) of thefrequency down-conversion portion, even if transistors in a deepsub-micron CMOS process having an inherently low output impedance areemployed as switching elements. For some applications, for instance foraudio and measurement applications, a frequency conversion is notneeded, so that the frequency down-conversion portion may be omitted Inthis case, the current mode signal output by the transconductanceportion is provided directly to the operational amplifier.

Advantageously, a gain control is provided, which adjusts thecapacitance in the feedback path of the operational amplifier inaccordance with a required gain.

The invention can be used for example in direct conversion or in any IFreceiver, e.g. in a low-IF receiver or a heterodyne receiver etc., ofany radio system.

The invention can be employed for example in RF circuits using digitalor analog CMOS technologies. In these cases, the transconductanceportion can be realized in particular with a mixer. When such a mixer issubstituted by a transconductor, the invention can also be integratedfor instance in audio or instrumentation circuits.

The invention is of particular advantage for a pure sub-micron digitalCMOS process, without any additional process options.

BRIEF DESCRIPTION OF THE FIGURES

Other objects and features of the present invention will become apparentfrom the following detailed description considered in conjunction withthe accompanying drawings.

FIG. 1 is a block diagram of a conventional direct conversion receiver;

FIG. 2 is a block diagram of a conventional digitized direct conversionreceiver;

FIG. 3 illustrates the principle of a current mode sampling;

FIG. 4 illustrates the principle of current mode sampling with frequencydown-conversion;

FIG. 5 illustrates a frequency down-conversion;

FIG. 6 illustrates the inherent anti-alias filtering of a current modesampling;

FIG. 7 is a schematic diagram of a known circuit for a passive currentmode sampling with frequency downconversion and active integrator;

FIG. 8 is a schematic diagram of a known circuit for a passive currentmode sampling with frequency downconversion and active low powerintegrator;

FIG. 9 is a schematic diagram of a known circuit for an active currentmode sampling with frequency downconversion;

FIG. 10 is a schematic diagram of a circuit for an active low powercurrent mode sampling with frequency downconversion according to anembodiment of the invention;

FIG. 11 is a schematic diagram of a circuit for an active low powercurrent mode sampling with gain control and frequency downconversionaccording to an embodiment of the invention;

FIG. 12 is a schematic diagram of a first possible gain control circuitfor the circuit of FIG. 11;

FIG. 13 is a schematic diagram of a second possible gain control circuitfor the circuit of FIG. 11; and

FIG. 14 is a flow chart illustrating the gain control in the circuit ofFIG. 13.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 10 is a schematic diagram of an exemplary circuit enabling anactive current mode sampling in accordance with the invention. Thecircuit can be implemented for example in a receiver 107.

The circuit of FIG. 10 comprises a transconductance element 100, forinstance in form of a mixer, a frequency down-conversion portion 101, asampling and LPF portion 102, and a following SC block 104, realizingfor example an ADC and/or some SC filter.

The transconductance element 100 has two inputs and two outputs, thelatter being connected to the frequency down-conversion portion 101. Thefrequency down-conversion portion 101 comprises switches which arecontrolled by signals LO+ and LO− of a local oscillator (not shown).

The sampling and LPF portion 102 comprises an operational amplifier 103.The first output of the frequency down-conversion portion 101 isconnected via a first input of the sampling and LPF portion 102 to afirst input of operational amplifier 103. A capacitor C1 a on the onehand and a series connection of a switch S101 a, a shared switchedcapacitor C2 a and a switch S102 a on the other hand are arranged inparallel to each other between the first input and a first output ofoperational amplifier 103. The connection between switch S101 a andcapacitor C2 a is connected via a switch S103 a to ground Vcm, while theconnection between capacitor C2 a and switch S102 a is connected via aswitch S104 a to a first output of the sampling and LPF portion 102.

The second output of the frequency down-conversion portion 101 isconnected via a second input of the sampling and LPF portion 102 to asecond input of operational amplifier 103. Corresponding components areconnected directly and indirectly to the second input and a secondoutput of operational amplifier 103 as to the first input and output ofoperational amplifier 103. Corresponding capacitors are named C1 b andC2 b instead of C1 a and C2 a, respectively, and corresponding switchesare named S101 b to S104 b instead of S101 a to S104 a, respectively.

In the following, the term capacitor C1 refers to either of capacitorsC1 a and C1 b, while the term capacitor C2 refers to either ofcapacitors C2 a and C2 b. Similarly, the term switch S101 refers toeither of switches S101 a and S101 b, the term switch S102 refers toeither of switches S102 a and S102 b, the term switch S103 refers toeither of switches S103 a and S103 b, and the term switch S104 refers toeither of switches S104 a and S104 b.

The components of the sampling and LPF portion 102 form an activeswitched-capacitor integrator.

The first output of the sampling and LPF portion 102 is connected withinthe SC block 104 to a first input of an operational amplifier 105. Thesecond output of the sampling and LPF portion 102 is connected withinthe SC block 104 to a second input of operational amplifier 105.

A respective capacitor C3 a, C3 b is arranged between the first inputand a first output of operational amplifier 105 and between the secondinput and a second output of operational amplifier 105. Further elementsmay be connected in parallel to the respective capacitor C3 a, C3 b, inorder to realize the desired function.

In addition, a common mode control portion 106 is provided, which isconnected to the connections between the frequency down-conversionportion 101 and the sampling and LPF portion 102. The common modecontrol portion 106 measures the common mode voltage of the operationalamplifier 103 and keeps this common mode voltage within a correctoperational range.

All switching elements are, by way of example, transistors realized in adeep sub-micron CMOS process.

Transconductance element 100 first converts two input RF voltage modesignals into RF current mode signals and provides them to the frequencydown conversion portion 101.

The local oscillator provides alternating signals LO+ and LO− to theswitches of the frequency down conversion portion 101. When the LO+signal is active, the outputs of the transconductance element 100 areconnected to the sampling and LPF portion 102 in a direct way, i.e. thefirst output of the transconductance element 100 is connected to thefirst path of the sampling and LPF portion 102, while the second outputof the transconductance element 100 is connected to the second path ofthe sampling and LPF portion 102. When the LO− signal is active, theoutputs of the transconductance element 100 are connected to thesampling and LPF portion 102 in a cross-coupled way, i.e. the firstoutput of the transconductance element 100 is connected to the secondpath of the sampling and LPF portion 102, while the second output of thetransconductance element 100 is connected to the first path of thesampling and LPF portion 102. With this operation, the RF currentsignals output by the transconductance element 100 are frequencydown-converted converted into base band current signals.

In the sampling and LPF portion 102, the received base band current modesignal is integrated by the combination of continuous time capacitor C1and shared switched capacitor C2, which are connected in parallel toeach other in the feedback loop of operational amplifier 103. SwitchesS101 and S102 are closed during a clock phase φ1, while switches S103and S104 are closed during a clock phase φ2. Clock phases φ1 and φ2 arealternating with each other. Capacitor C2 is therefore only chargedduring a respective clock phase φ1.

The signal voltage at the operational amplifier 103 output is alsoavailable across shared switched capacitor C2. Therefore it is possibleto use capacitor C2 to transfer a charge to the following SC block 104during a respective clock phase φ2 in between the charging clock phasesφ1. When the charge from capacitor C2 is transferred to the following SCblock 104 during a respective clock phase φ2, it is simultaneouslydischarged and, thus, no additional reset phases and switches areneeded.

Capacitors C2 a and C2 b are referred to as shared switched capacitors,since in a conventional circuit topology, additional separate samplingcapacitors are employed, which are usually connected to the output ofthe operational amplifier, like capacitors C4 a and C4 b in FIG. 9.Because such separate sampling capacitors are omitted in the inventivecircuit, the capacitive load of the operational amplifier 103 isreduced. This results in a lower power consumption compared to aconventional active current mode sampling, like the active current modesampling in the circuit of FIG. 9. Since the total number of thecomponents in the sampling circuitry is moreover smaller than in aconventional circuit, the total thermal noise contribution of thesampling capacitors (kT/C) is also reduced.

It is another advantage of the sampling circuit of FIG. 10 that voltagemode error signals of the operational amplifier 103, such as 1/f noise,DC offset and settling errors, are not sampled in full. The integratedsample, which is converted back into a voltage mode signal in samplingcapacitor C2 and which is transferred to the following SC block 104,contains only a fraction of operational amplifier related errorscompared to conventional circuits. The reason is that these errors arenot sampled by capacitor C2, as capacitor C2 is connected between inputand output of operational amplifier 103. In a conventional circuit, incontrast, such errors are sampled by the separate sampling capacitor,since such a separate sampling capacitor is connected only to the outputof the operational amplifier.

In the circuit of FIG. 10, the operational amplifier related errors seea gain close to unity, as the source impedance formed by thetransconductance element 100 and mixer 101 is relatively high comparedto the impedances that define the gain. On the other hand, the signalgain can be set independently from the noise gain with the product ofthe voltage gain of an LNA (not shown) arranged before thetransconductance element 100, the transconductance of thetransconductance element 100 and the effective resistance of sharedswitched capacitor C2. Thus, some of the requirements on the operationalamplifier 103 are relaxed. This enables a more cost-effectiveimplementation, as the error contribution of the operational amplifieris negligible in the inventive sampling scheme.

FIG. 11 presents an active current mode sampling circuit, in which thesignal gain can be controlled. The circuit is identical to the one inFIG. 10, except that gain controlled SC circuits 110 are provided, whichrealize the functions of the capacitors C1 and C2 and the switches S101to S104 of FIG. 10 in a way that the signal gain can be controlled. Thegain controlled SC circuits 110 have a first terminal A connected to aninput of operational amplifier 103, a second terminal B connected to anoutput of operational amplifier 103, and a third terminal C connected toan output of the sampling and LPF portion 102. In addition, a gaincontrol portion 111 is provided, which provides gain setting signals Gn,XGn to the gain controlled SC circuits 110 in accordance with a desiredgain. Each of the gain setting signals XGn is an inverted version of therespective gain setting signal Gn. For example, when G1=1 then XG1=0. Inthe following examples, the schematics are drawn and the gain settingsignals are defined in such a way that the gain setting signals Gncontrol the attenuation.

A gain control can be added to the current mode sampling by simplycontrolling the value of the sampling capacitor C2 of FIG. 10 in thegain controlled SC circuit 110 of FIG. 11. However, changing the valueof the sampling capacitor C2 also moves the corner frequency of theentire SC integrator of the sampling and LPF portion 102.

If the frequency response of the SC integrator is required to stayconstant, the ratio of the shared sampling capacitor C2 and thecontinuous time capacitor C1 has to be kept constant. This can beachieved with a gain control which is shown in detail in FIG. 12, andwhich can be used in the gain controlled SC circuit 110 of the currentmode sampling circuit of FIG. 11.

In FIG. 12, capacitor C1 is arranged between terminals A and B, and aseries connection of switch S101, capacitor C2 and switch S102 arearranged in parallel to capacitor C1. The connection between switch S101and capacitor C2 is connected via a switch S103 to ground Vcm, and theconnection between capacitor C2 and switch S102 is connected via aswitch S104 to terminal C. As in FIG. 10, switches S101 and S102 areclosed during clock phases φ1, while switches S103 and S104 are closedduring clock phases φ2.

In addition, a series connection of a switch S121.1, a capacitor C1.1and a switch S122.1 is arranged between terminals A and B, in parallelwith a series connection of a switch S123.1, a capacitor C2.1 and aswitch S124.1. The connection between switch S123.1 and capacitor C2.1is connected via a switch S125.1 to ground Vcm, and the connectionbetween capacitor C2.1 and switch S124.1 is connected via a switchS126.1 to ground Vcm. Switches S121.1 and S122.1 are closed constantlyin case of a gain setting signal G1, switches S123.1 and S124.1 areclosed in case of a gain setting signal G1 during clock phases φ1, andswitches S125.1 and S126.1 are closed in case of a gain setting signalXG1 or during clock phases φ2. Alternatively, switches S125.1 and S126.1could be closed only in case of a gain setting signal XG1 during clockphases φ2. The difference is that capacitor C2.1 would not be shortcircuited to ground Vcm when G1 is not active, instead it would befloating.

Further in addition, a series connection of a switch S121.2, a capacitorC1.2 and a switch S122.2 is arranged between terminals A and B, inparallel with a series connection of a switch S123.2, a capacitor C2.2and a switch S124.2. The connection between switch S123.2 and capacitorC2.2 is connected via a switch S125.2 to ground Vcm, and the connectionbetween capacitor C2.2 and switch S124.2 is connected via a switchS126.2 to ground Vcm. Switches S121.2 and S122.2 are closed in case of again setting signal G2, switches S123.2 and S124.2 are closed in case ofa gain setting signal G2 during clock phases φ1, and switches S125.2 andS126.2 are closed in case of a gain setting signal XG2 or during clockphases φ2.

Further similar arrangements of capacitors C1.n and C2.n, with n=3 to N,are added in parallel between terminals A and B. These capacitors C1.nand C2.n are switched based on gain setting signals Gn and XGn, with n=3to N, just like capacitors C1.1, C2.1, C1.2 and C2.2 are switched basedon gain setting signals G1, XG1, G2 and XG2.

The value of capacitors C1.n, with n=1 to N, is the same as the value ofcapacitor C1, and the value of capacitors C2.n, with n=1 to N, is thesame as the value of capacitor C2. Thus, the largest total capacitanceCtot which can be added to the original capacitance by providing gainsetting signals G1, XG1, G2 and XG2 etc. is Ctot=N*(C1+C2). Thecomponents enabling the gain control are placed in FIG. 12 within arectangle 120.

A drawback of a gain control of FIG. 12 is that if a large attenuationis needed in the gain control circuit, the size of both the continuoustime capacitor C1 and the switched capacitor C2 will become very large.

An improved kind of gain control resulting in a smaller capacitor area,which can equally be used in the gain controlled SC circuit 110 of FIG.11, is shown in FIG. 13.

In this approach, a certain total capacitance Ctot of Ctot=C1+C2 isused. The shared sampling capacitor C2 is divided in to N smaller unitsC2.n, with n=1 to N, such that C2=C2.1+C2.2+ . . . +C2.N.

In the circuit of FIG. 13, capacitor C1 is arranged again betweenterminals A and B. N series connections of a switch S131.n, a capacitorC2.n and a switch S132.n, with n=1 to N, are connected in parallel tocapacitor C1. The connection between a respective switch S131.n and arespective capacitor C2.n is connected via a respective switch S133.n,with n=1 to N, to ground Vcm. The connection between a respectivecapacitor C2.n and a respective switch S132.n is connected on the onehand via a switch S134.n, with n=1 to N, to ground Vcm, and on the otherhand via a switch 135.n, with n=1 to N, to terminal C. The componentsenabling the gain control are placed in FIG. 12 within a rectangle 130.

The switching of the capacitors C2.n in the gain control of FIG. 13 isillustrated in the flow chart of FIG. 14.

Switches S131.n and 132.n are closed during a respective charging clockphase φ1 so that all capacitors C2.n are switched between input andoutput of operational amplifier 103. During the charging clock phase φ1,thus the entire capacitor C2 is connected in parallel to capacitor C1and charged. At the same time, all other switches S133.n to S135.n areopened.

During a subsequent discharging clock phases φ2, switches S131.n and132.n are then opened again. Instead, switches 133.n are closed duringthis discharging clock phases φ2. Switches 134.n are closed during clockphases φ2, if at the same time a corresponding gain setting signal Gn,with n=1 to N, is present. Switches 135.n are closed during clock phasesφ2, if at the same time a corresponding gain setting signal XGn, withn=1 to N, is present. Thus, a capacitor C2.n is connected with bothterminals to ground, if a gain setting signal Gn is present, whichresults in a pure discharging of this capacitor C2.n. A capacitor C2.nis switched between ground and SC block 104, in contrast, if a gainsetting signal XGn is present, whereby the charge of the capacitor C2.nis transferred to SC block 104, while the capacitor C2.n is dischargedat the same time.

Thus, the number of the capacitor units C2.n transferring the integratedsignal to the following SC block 104 is controlled with the gain settingsignals G1, XG1, G2 and XG2, etc.

It is to be noted that the described embodiment constitutes only one ofa variety of possible embodiments of the invention.

1. Active current mode sampling circuit comprising: an operationalamplifier; at least one switched capacitor; first switching elements forswitching said at least one switched capacitor between an input and anoutput of said operational amplifier during charging phases and fordisconnecting said at least one switched capacitor from said input andsaid output of said operational amplifier in between said chargingphases; and second switching elements for connecting said at least oneswitched capacitor during discharging phases in between said chargingphases to a subsequent stage, in order to provide a charge of said atleast one switched capacitor to said subsequent stage, and fordisconnecting said at least one switched capacitor from said subsequentstage, respectively, in between said discharging phases.
 2. Activecurrent mode sampling circuit according to claim 1, wherein said atleast one switched capacitor includes a first switched capacitor whichis switched by said switching elements between a first input and a firstoutput of said operational amplifier during said charging phases, and asecond switched capacitor which is switched by said switching elementsbetween a second input and a second output of said operational amplifierduring said charging phases.
 3. Active current mode sampling circuitaccording to claim 1, further comprising at least one continuous timecapacitor, which at least one continuous time capacitor is connectedfixedly to an input and an output of said operational amplifier. 4.Active current mode sampling circuit according to claim 3, furthercomprising at least one pair of a further switched capacitor and afurther continuous time capacitor, both arranged in parallel to said atleast one switched capacitor and to said at least one continuous timecapacitor; and switching elements for connecting a continuous timecapacitor of selected pairs of a further switched capacitor and afurther continuous time capacitor continuously between said input andsaid output of said operational amplifier; switching elements forswitching a switched capacitor of said selected pairs of a furtherswitched capacitor and a further continuous time capacitor between saidinput and said output of said operational amplifier during said chargingphases and for disconnecting said at least one switched capacitor fromsaid input and said output of said operational amplifier in between saidcharging phases; and switching elements for switching a switchedcapacitor of said selected pairs of a further switched-capacitor and afurther continuous time capacitor on both sides to ground during saiddischarging phases.
 5. Active current mode sampling circuit according toclaim 4, further comprising a gain control portion for selecting saidpairs of a further switched capacitor and a further continuous timecapacitor in accordance with a required gain.
 6. Active current modesampling circuit according to claim 1, wherein said at least oneswitched capacitor is divided into a plurality of switched capacitorunits connected in parallel to each other, said second switchingelements being controlled for connecting selected ones of said switchedcapacitor units to said subsequent stage during said discharging phases.7. Active current mode sampling circuit according to claim 6, furthercomprising a gain control portion for selecting said switched capacitorunits in accordance with a required gain.
 8. Active current modesampling circuit according to claim 1, further comprising atransconductance portion for converting a received voltage mode signalinto a current mode signal and for providing said current mode signal toan input of said operational amplifier.
 9. Active current mode samplingcircuit according to claim 1, further comprising a transconductanceportion for converting a received voltage mode signal into a currentmode signal; and a frequency down-conversion portion for frequencydown-converting a current mode signal output by said transconductanceportion and for providing said frequency down-converted current modesignal to an input of said operational amplifier.
 10. Device comprisingan active current mode sampling circuit according to claim
 1. 11. Methodof operating an active current mode sampling circuit, which activecurrent mode sampling circuit includes an operational amplifier and atleast one switched capacitor, said method comprising: switching said atleast one switched capacitor between an input and an output of saidoperational amplifier during charging phases; disconnecting said atleast one switched capacitor from said input and said output of saidoperational amplifier in between said charging phases; connecting saidat least one switched capacitor during discharging phases in betweensaid charging phases to a subsequent stage, in order to provide a chargeof said at least one switched capacitor to said subsequent stage; anddisconnecting said at least one switched capacitor from said subsequentstage in between said discharging phases.
 12. Method according to claim11, wherein said at least one switched capacitor includes a firstswitched capacitor and a second switched capacitor, said methodcomprising switching said first switched capacitor between a first inputand a first output of said operational amplifier during said chargingphases, and switching said second switched capacitor between a secondinput and a second output of said operational amplifier during saidcharging phases.
 13. Method according to claim 11, wherein said activecurrent mode sampling circuit further includes at least one continuoustime capacitor which is connected fixedly to an input and an output ofsaid operational amplifier, and at least one pair of a further switchedcapacitor and a further continuous time capacitor, both arranged inparallel to said at least one switched capacitor and to said at leastone continuous time capacitor, said method further comprising connectinga continuous time capacitor of selected pairs of a further switchedcapacitor and a further continuous time capacitor continuously betweensaid input and said output of said operational amplifier; switching aswitched capacitor of said selected pairs of a further switchedcapacitor and a further continuous time capacitor between said input andsaid output of said operational amplifier during said charging phases,and disconnecting said at least one switched capacitor from said inputand said output of said operational amplifier in between said chargingphases; and switching a switched capacitor of said selected pairs of afurther switched capacitor and a further continuous time capacitor onboth sides to ground during said discharging phases.
 14. Methodaccording to claim 13, further comprising selecting said pairs of afurther switched capacitor and a further continuous time capacitor inaccordance with a required gain.
 15. Method according to claim 11,wherein said at least one switched capacitor is divided into a pluralityof switched capacitor units connected in parallel to each other, saidconnecting of said at least one switched capacitor to a subsequent stageduring said discharging phases comprising connecting selected ones ofsaid switched capacitor units to a subsequent stage during saiddischarging phases.
 16. Method according to claim 15, further comprisingselecting said switched capacitor units in accordance with a requiredgain.
 17. Method according to claim 11, further comprising converting areceived voltage mode signal into a current mode signal and providingsaid current mode signal to an input of said operational amplifier. 18.Method according to claim 11, further comprising converting a receivedvoltage mode signal into a current mode signal, frequencydown-converting said current mode signal and providing said frequencydown-converted current mode signal to an input of said operationalamplifier.
 19. Apparatus comprising: means for switching said at leastone switched capacitor between an input and an output of saidoperational amplifier during charging phases; means for disconnectingsaid at least one switched capacitor from said input and said output ofsaid operational amplifier in between said charging phases; means forconnecting said at least one switched capacitor during dischargingphases in between said charging phases to a subsequent stage, in orderto provide a charge of said at least one switched capacitor to saidsubsequent stage; and means for disconnecting said at least one switchedcapacitor from said subsequent stage in between said discharging phases.20. The apparatus of claim 19, further comprising means for switchingsaid first switched capacitor between a first input and a first outputof said operational amplifier during said charging phases, and means forswitching said second switched capacitor between a second input and asecond output of said operational amplifier during said charging phases.